In recent years, there have been widely used video cameras and electronic cameras. Each of these cameras adopts a solid-state imaging device such as a CCD (Charge Coupled Device) or a CMOS (Complementary Metal Oxide Semiconductor) image sensor. Such a solid-state imaging device includes an imaging block in which a plurality of photoelectric conversion blocks each configured by a photodiode are disposed in a two-dimensional array, and there are formed unit regions (unit pixels) each including the photodiode as a main functional part.
In the CCD, a light beam incident on each unit pixel is photoelectric-converted by a photodiode into a signal charge, which is transferred to a floating diffusion (FD) block provided at an output block via a vertical CCD transfer register as well as via a horizontal CCD transfer register. Thereafter, with use of a MOS transistor, the CCD senses a variation in electric potential of the FD block and amplifies the sensed variation in electric potential so as to output as an imaging signal.
By the way, the CMOS image sensor includes in each unit pixel an FD block as well as various types of MOS transistors used for transfer, amplification, and the like, and accordingly does not need to transfer an electric charge. The CMOS image sensor is thus operable at a lower voltage in comparison to a CCD-type solid-state imaging device, and is suited to reduction in electric power consumption. The CMOS image sensor is also suited to reduction in size of the image sensor since complicated signal processing functions can be easily aggregated in one chip.
FIG. 12 is an explanatory view exemplifying a configuration of an imaging block of a conventional CMOS image sensor with an equivalent circuit for one unit pixel. In the CMOS image sensor shown in FIG. 12, each unit pixel 100 includes a photoelectric conversion block configured by a photodiode 102 and four MOS transistors 103 and 105 to 107 for converting a signal charge into a voltage signal and outputting the obtained voltage signal (see Patent Document 1 or the like).
During light receiving operation, signal charges (electrons) accumulated in the photodiode 102 are transferred to a floating diffusion (FD) block 104 through the electric charge transfer gate 103 in accordance with a readout pulse that is applied from a readout signal line 109 to a gate electrode of the electric charge transfer gate 103. The FD block 104 is connected to a gate electrode of the amplifier transistor 105, and a variation in electric potential of the FD block 104 due to the signal charges (electrons) is impedance-converted by the amplifier transistor 105 and is then outputted to a vertical signal line 15. The vertical select transistor 106 is switched ON and OFF in accordance with a vertical select pulse that is applied from a vertical select line 13 to a gate electrode thereof so as to drive the amplifier transistor 105 for a predetermined period of time. The reset transistor 107 resets the electric potential of the FD block 104 so as to be equal to the electric potential of a power supply line 108 in accordance with a vertical reset pulse that is applied from a vertical reset line 14 to the gate electrode thereof.
The unit pixels 100 are scanned as follows, one time each in one cycle by a vertical shift register 11 as well as by a horizontal shift register 12. Specifically, when vertical select pulses are outputted from the vertical shift register 11 to one vertical select line 13 during a constant period of time in one cycle, there are selected pixels in a row corresponding to this vertical select line 13, and output signals of the respective pixels are outputted to the corresponding vertical signal lines 15. During this constant period of time, horizontal select pulses are sequentially outputted from the horizontal shift register 12 to the respective horizontal select lines 17, and the output signals from the corresponding vertical signal lines 15 are sequentially extracted to horizontal signal lines 18 through the horizontal select transistors 16, respectively. Upon completion of scanning all the pixels in the same row, vertical select pulses are outputted to the vertical select line 13 in the following row so as to scan the respective pixels in the following row in the way similar to the above. These operations are repeated to scan all the pixels in all the rows one time each during one cycle, and there is performed time-series extraction of the output signals thereof to the respective horizontal signal lines 18.
FIG. 13 is a cross sectional view showing a configuration of the imaging block in the conventional CMOS image sensor. FIG. 14 is an explanatory view conceptually showing a relation of connection between the FD block 104 and peripheral impurity layers thereof, which cannot be fully shown in the cross sectional view of FIG. 13.
As shown in FIG. 13, there are formed in a surface layer of a silicon substrate 101 photodiodes 102 respectively embedded therein. Formed in the peripheries thereof is an n-type impurity layer that configures the MOS transistors inclusive of the electric charge transfer gates 103. As shown in FIG. 14, the n-type impurity layer configuring the embedded photodiode 102, the FD block 104, and the reset transistor 107 is provided and is electrically connected by a channel region below the gate electrode, thereby realizing effective transfer and elimination of a signal charge.
Leakage of a light beam into the circuit block including the MOS transistors causes photoelectric conversion, and a resultant electron generates an aliasing, which works as a noise.
There is formed a multilayer interconnection made of aluminum or the like above the silicon substrate 101 in an insulative layer 124 made of silicon oxide or the like. This multilayer interconnection includes a first layer of interconnection 121 which may be locally provided for connecting pixel transistors with each other, and a second layer of interconnection 122 as well as a third layer of interconnection 123, each of which may be provided in a wider area as a control signal line such as the vertical select line 13 for driving the transistors described above, a signal line such as the vertical signal line 15 for transmitting an electrical signal amplified by the amplifier transistor 105, a power supply line, or the like.
Further formed above the multilayer interconnection are a passivation film 125 made of silicon nitride or the like, a planarizing film, and the like, on top of which there are disposed a pixel color filter 126 and on-chip lenses 127. The on-chip lenses 127 are each used for condensing an incident light beam on the corresponding photodiode 102, and are generally provided at constant intervals so as to be equally spaced apart from one another.
In the above CMOS image sensor, the unit pixels 100 each have in common a relative positional relation among the photodiode 102, the MOS transistors 103 and 105 to 107, the in-pixel interconnection, and the on-chip lens 127. In other words, these respective members are disposed at constant intervals so as to be equally spaced apart from one another, thereby having same translational symmetry. As a result, a light beam is made incident on the photodiode 102 similarly in each of the unit pixels 100 so as to obtain an excellent image with less variations among the respective unit pixels 100.
An amplification-type solid-state image sensor such as a CMOS image sensor is required to include a multilayer interconnection of at least two layers, and desirably of three or more layers, as described above, which are formed on the photodiodes 102 with a large thickness. The difference in height between the surfaces of the photodiodes 102 and the third uppermost layer of interconnection may be 2 μm to 5 μm, which is substantially equal to one side of each of the pixels. A solid-state imaging device, which obtains an image by capturing a target subject with a lens, has a problem of large shading in a region close to the periphery of an imaged area, that is, interruption of an obliquely incident light beam by a light shielding film or by an interconnection, which reduces the quantity of light beams condensed on the photodiodes to result in significant deterioration in image quality.
In order to make such an obliquely incident light beam also condensed on a photodiode in the region close to the periphery of the imaged area, shading may be reduced by correcting the positions of the on-chip lens and the opening in the light shielding film, which is referred to as pupil correction. More specifically, the on-chip lens and the opening in the light shielding film are disposed in a direction along the incident light beam when seen from the photodiode. Patent Document 2 to be described later proposes a solid-state image sensor in which the position of a signal line (interconnection) relative to each unit pixel is deflected toward the center of an imaged area gradually from the center to the periphery of the imaged area.
In the present application, a unit region (unit pixel) indicates a region on a substrate provided with a portion for realizing a main function of one photodiode. Translational symmetry in an array of unit regions indicates regularity in the array that is obtained by collection of points each occupying a fixed position (such as a center) within unit regions equally sized.
In recent years, reduction in size of a solid-state image sensor has been required more for the purpose of mounting a camera function onto a mobile apparatus such as a mobile phone. Such reduction in size of the solid-state image sensor as well as reduction in size of each unit pixel for the purpose of increase in the number of pixels cause reduction in light receiving area in one unit pixel, which results in deterioration in properties of the solid-state image sensor such as the quantity of saturation signals and sensitivity.
In order to prevent such deterioration in properties, there has been conventionally adopted a countermeasure of reducing the area of transistors within a unit pixel so as to prevent reduction in area of a photodiode. However, it has been difficult to preferably maintain the properties of the solid-state image sensor with such a countermeasure.    Patent Document 1: Japanese Unexamined Patent Application No. 2006-303468    Patent Document 2: Japanese Unexamined Patent Application No. 2003-273342    Patent Document 3: Japanese Unexamined Patent Application No. 2005-198001    Patent Document 4: U.S. Pat. No. 6,043,478